Symmetry and Synchronous Verilog

Synchronous verilog has a type declaration mechanism that makes it possible to use symmetry reductions (see section 4.4) with synchronous verilog programs. Since bit vectors are generally used to represent scalars in verilog programs, synchronous verilog uses scalarset bit vectors (see section 4.11) as its symmetric types. For example, to declare a symmetric bit vector type foo with four bits, use the following declaration:

  scalarset [3:0] foo;

An ordered type can be similarly declared:

  ordset [3:0] foo;

An asymmetric type can also be declared, as follows:

  typedef [3:0] foo;

A variable of this type can be declared as follows:

  reg foo varname;

or

  wire foo varname;

To introduce code that breaks the symmetry of type foo, we use the syntax:

  breaking(foo)
    ...code breaking symmetry of type foo...
  endbreaking