Peripherials:

Last Measured Battery Voltage This register may be read while BATUPD.STAT = 1

[10:8] Integer part: 0x0: 0V + fractional part ... 0x3: 3V + fractional part 0x4: 4V + fractional part

[7:0] Fractional part, standard binary fractional encoding. 0x00: .0V ... 0x20: 1/8 = .125V 0x40: 1/4 = .25V 0x80: 1/2 = .5V ... 0xA0: 1/2 + 1/8 = .625V ... 0xFF: Max

Battery Update Indicates BAT Updates

[0:0] 0: No update since last clear 1: New battery voltage is present. Write 1 to clear the status.

Temperature Last Measured Temperature in Degrees Celsius This register may be read while TEMPUPD.STAT = 1.

[16:8] Integer part (signed) of temperature value. Total value = INTEGER + FRACTIONAL 2's complement encoding 0x100: Min value 0x1D8: -40C 0x1FF: -1C 0x00: 0C 0x1B: 27C 0x55: 85C 0xFF: Max value

Temperature Update Indicates TEMP Updates

[0:0] 0: No update since last clear 1: New temperature is present. Write 1 to clear the status.

Wake-up Selector For MCU This register contains pointers to 4 events which are routed to AON_WUC as wakeup sources for MCU. AON_WUC will start a wakeup sequence for the MCU domain when either of the 4 selected events are asserted. A wakeup sequence will guarantee that the MCU power switches are turned on, LDO resources are available and SCLK_HF is available and selected as clock source for MCU. Note: It is recommended ( or required when AON_WUC:MCUCLK.PWR_DWN_SRC=NONE) to also setup a wakeup event here before MCU is requesting powerdown. ( PRCM requests uLDO, see conditions in PRCM:VDCTL.ULDO ) as it will speed up the wakeup procedure.

[29:24] MCU Wakeup Source #3 AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the MCU domain from Power Off or Power Down. Note:

[21:16] MCU Wakeup Source #2 AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the MCU domain from Power Off or Power Down. Note:

[13:8] MCU Wakeup Source #1 AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the MCU domain from Power Off or Power Down. Note:

[5:0] MCU Wakeup Source #0 AON Event Source selecting 1 of 4 events routed to AON_WUC for waking up the MCU domain from Power Off or Power Down. Note:

Wake-up Selector For AUX This register contains pointers to 3 events which are routed to AON_WUC as wakeup sources for AUX. AON_WUC will start a wakeup sequence for the AUX domain when either of the 3 selected events are asserted. A wakeup sequence will guarantee that the AUX power switches are turned on, LDO resources are available and SCLK_HF is available and selected as clock source for AUX. Note: It is recommended ( or required when AON_WUC:AUXCLK.PWR_DWN_SRC=NONE) to also setup a wakeup event here before AUX is requesting powerdown. ( AUX_WUC:PWRDWNREQ.REQ is asserted] ) as it will speed up the wakeup procedure.

[21:16] AUX Wakeup Source #2 AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the AUX domain from Power Off or Power Down. Note:

[13:8] AUX Wakeup Source #1 AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the AUX domain from Power Off or Power Down. Note:

[5:0] AUX Wakeup Source #0 AON Event Source selecting 1 of 3 events routed to AON_WUC for waking up the AUX domain from Power Off or Power Down. Note:

Event Selector For MCU Event Fabric This register contains pointers for 3 AON events that are routed to the MCU Event Fabric EVENT

[21:16] Event selector for AON_PROG2 event. AON Event Source id# selecting event routed to EVENT as AON_PROG2 event.

[13:8] Event selector for AON_PROG1 event. AON Event Source id# selecting event routed to EVENT as AON_PROG1 event.

[5:0] Event selector for AON_PROG0 event. AON Event Source id# selecting event routed to EVENT as AON_PROG0 event.

RTC Capture Event Selector For AON_RTC This register contains a pointer to select an AON event for RTC capture. Please refer to AON_RTC:CH1CAPT

[5:0] AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer to AON_RTC:CH1CAPT

IO Latch Control Controls transparency of all latches holding I/O or configuration state from the MCU IOC

[0:0] Controls latches between MCU IOC and AON_IOC. The latches are transparent by default. They must be closed prior to power off the domain(s) controlling the IOs in order to preserve IO values on external pins.

SCLK_LF External Output Control

[0:0] 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. IOC:IOCFG0.PORT_ID) set to AON_CLK32K. 1: Output enable not active

Control This register contains various bitfields for configuration of RTC

[18:16] Eventmask selecting which delayed events that form the combined event.

[11:8] Number of SCLK_LF clock cycles waited before generating delayed events. (Common setting for all RTC cannels) the delayed event is delayed

[7:7] RTC Counter reset. Writing 1 to this bit will reset the RTC counter. This bit is cleared when reset takes effect

[2:2] RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 which is used by AUX timer. 0: RTC_4KHZ signal is forced to 0 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN)

[1:1] RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is SCLK_LF divided by 2 0: RTC_UPD signal is forced to 0 1: RTC_UPD signal is toggling @16 kHz

[0:0] Enable RTC counter 0: Halted (frozen) 1: Running

Event Flags, RTC Status This register contains event flags from the 3 RTC channels. Each flag will be cleared when writing a '1' to the corresponding bitfield.

[16:16] Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or passes the CH2CMP value. An event will be scheduled to occur as soon as possible when writing to CH2CMP provided that the channel is enabled and the new value matches any time between next RTC value and 1 second in the past Writing 1 clears this flag. Note that a new event can not occur on this channel in first 2 SCLK_LF cycles after a clearance. AUX_SCE can read the flag through AUX_WUC:WUEVFLAGS.AON_RTC_CH2 and clear it using AUX_WUC:WUEVCLR.AON_RTC_CH2.

[8:8] Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP value. - CHCTL.CH1_CAPT_EN = 1 and capture occurs. An event will be scheduled to occur as soon as possible when writing to CH1CMP provided that the channel is enabled, in compare mode and the new value matches any time between next RTC value and 1 second in the past. Writing 1 clears this flag. Note that a new event can not occur on this channel in first 2 SCLK_LF cycles after a clearance.

[0:0] Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or passes the CH0CMP value. An event will be scheduled to occur as soon as possible when writing to CH0CMP provided that the channels is enabled and the new value matches any time between next RTC value and 1 second in the past. Writing 1 clears this flag. Note that a new event can not occur on this channel in first 2 SCLK_LF cycles after a clearance.

Second Counter Value, Integer Part

[31:0] Unsigned integer representing Real Time Clock in seconds. When reading this register the content of SUBSEC.VALUE is simultaneously latched. A consistent reading of the combined Real Time Clock can be obtained by first reading this register, then reading SUBSEC register.

Second Counter Value, Fractional Part

[31:0] Unsigned integer representing Real Time Clock in fractions of a second (VALUE/2^32 seconds) at the time when SEC register was read. Examples : - 0x0000_0000 = 0.0 sec - 0x4000_0000 = 0.25 sec - 0x8000_0000 = 0.5 sec - 0xC000_0000 = 0.75 sec

Subseconds Increment Value added to SUBSEC.VALUE on every SCLK_LFclock cycle.

[23:0] This value compensates for a SCLK_LF clock which has an offset from 32768 Hz. The compensation value can be found as 2^38 / freq, where freq is SCLK_LF clock frequency in Hertz This value is added to SUBSEC.VALUE on every cycle, and carry of this is added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a hidden 6-bit register that generates a carry into the above mentioned addition on overflow. The default value corresponds to incrementing by precisely 1/32768 of a second. NOTE: This register is read only. Modification of the register value must be done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and AUX_WUC:RTCSUBSECINCCTL

Channel Configuration

[18:18] Set to enable continuous operation of Channel 2

[16:16] RTC Channel 2 Enable 0: Disable RTC Channel 2 1: Enable RTC Channel 2

[9:9] Set Channel 1 mode 0: Compare mode (default) 1: Capture mode

[8:8] RTC Channel 1 Enable 0: Disable RTC Channel 1 1: Enable RTC Channel 1

[0:0] RTC Channel 0 Enable 0: Disable RTC Channel 0 1: Enable RTC Channel 0

Channel 0 Compare Value

[31:0] RTC Channel 0 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to 2 SCLK_LF clock cycles before event occurs due to synchronization.

Channel 1 Compare Value

[31:0] RTC Channel 1 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to 2 SCLK_LF clock cycles before event occurs due to synchronization.

Channel 2 Compare Value

[31:0] RTC Channel 2 compare value. Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of the compare value. The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE (31:16) values of the Real Time Clock register. A Cannel 0 event is generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or exciting the compare value. Writing to this register can trigger an immediate*) event in case the new compare value matches a Real Time Clock value from 1 second in the past up till current Real Time Clock value. Example: To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 *) It can take up to 2 SCLK_LF clock cycles before event occurs due to synchronization.

Channel 2 Compare Value Auto-increment This register is primarily used to generate periodical wake-up for the AUX_SCE module, through the [AUX_EVCTL.EVSTAT0.AON_RTC] event.

[31:0] If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every channel 2 compare event.

Channel 1 Capture Value If CHCTL.CH1_EN = 1and CHCTL.CH1_CAPT_EN = 1, capture occurs on each rising edge of the event selected in AON_EVENT:RTCSEL.

[31:16] Value of SEC.VALUE bits 15:0 at capture time.

[15:0] Value of SUBSEC.VALUE bits 31:16 at capture time.

AON Synchronization This register is used for synchronizing between MCU and entire AON domain.

[0:0] This register will always return 0,- however it will not return the value until there are no outstanding write requests between MCU and AON Note: Writing to this register prior to reading will force a wait until next SCLK_LF edge. This is recommended for syncing read registers from AON when waking up from sleep Failure to do so may result in reading AON values from prior to going to sleep

Power Management This register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled.

[2:2] Select to use DCDC regulator for VDDR in active mode 0: Use GLDO for regulation of VDDRin active mode. 1: Use DCDC for regulation of VDDRin active mode.

[1:1] Status of source for VDDRsupply: 0: DCDC/GLDO are generating VDDR 1: DCDC/GLDO are bypassed, external regulator supplies VDDR

[0:0] Select to use DCDC regulator during recharge of VDDR 0: Use GLDO for recharge of VDDR 1: Use DCDC for recharge of VDDR Note: This bitfield should be set to the same as DCDC_ACTIVE

Reset Management This register contains bitfields releated to system reset such as reset source and reset request and control of brown out resets.

[31:31] Cold reset register. Writing 1 to this bitfield will reset the entire chip and cause boot code to run again. 0: No effect 1: Generate system reset. Appears as SYSRESET in RESET_SRC.

[15:15] A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin being forced low) Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup sources. 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC 1: A wakeup has occurred from SHUTDOWN Note: This flag can not be cleared and will therefor remain valid untill poweroff/reset

[14:14] A wakeup from SHUTDOWN on an IO event has occurred Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup sources. 0: The wakeup did not occur from SHUTDOWN on an IO event 1: A wakeup from SHUTDOWN occurred from an IO event The case where WU_FROM_SD is asserted but this bitfield is not asserted will only occur in a debug session. The boot code will not proceed with wakeup from SHUTDOWN procedure until this bitfield is asserted as well. Note: This flag can not be cleared and will therefor remain valid untill poweroff/reset

[11:11] Override of VDDS_LOSS_EN 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN=1 1: Brown out detect of VDDS generates system reset (regardless of VDDS_LOSS_EN) This bit can be locked

[10:10] Override of VDDR_LOSS_EN 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN=1 1: Brown out detect of VDDR generates system reset (regardless of VDDR_LOSS_EN) This bit can be locked

[9:9] Override of VDD_LOSS_EN 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN=1 1: Brown out detect of VDD generates system reset (regardless of VDD_LOSS_EN) This bit can be locked

[7:7] Controls reset generation in case VDDS is lost 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 1: Brown out detect of VDDS generates system reset

[6:6] Controls reset generation in case VDDR is lost 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 1: Brown out detect of VDDR generates system reset

[5:5] Controls reset generation in case VDD is lost 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 1: Brown out detect of VDD generates system reset

[4:4] Controls reset generation in case SCLK_LF is lost. (provided that clock loss detection is enabled by DDI_0_OSC:CTL0.CLK_LOSS_EN) Note: Clock loss reset generation must be disabled before SCLK_LF clock source is changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain disabled untill the change is confirmed in DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do so may result in a spurious system reset. Clock loss reset generation can be disabled through this bitfield or by clearing DDI_0_OSC:CTL0.CLK_LOSS_EN 0: Clock loss is ignored 1: Clock loss generates system reset

[3:1] Shows the source of the last system reset: Occurrence of one of the reset sources may trigger several other reset sources as essential parts of the system are undergoing reset. This field will report the root cause of the reset (not the other resets that are consequence of the system reset). To support this feature the actual register is not captured before the reset source being released. If a new reset source is triggered, in a window of four 32 kHz periods after the previous has been released, this register may indicate Power on reset as source.

Sleep Mode This register is used to unfreeze the IO pad ring after waking up from SHUTDOWN

[0:0] Controls the I/O pad sleep mode. The boot code will set this bitfield automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set ). 0: I/O pad sleep mode is enabled, ie all pads are latched and can not toggle. 1: I/O pad sleep mode is disabled Application software may want to reconfigure the state for all IO's before setting this bitfield upon waking up from a SHUTDOWN.

MCU Clock Management This register contains bitfields related to the MCU clock.

[2:2] MCU bootcode will set this bit when RCOSC_HF is calibrated. The FLASH can not be used until this bit is set. 1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up. 0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF is safe

[1:0] Controls the clock source for the entire MCU domain while MCU is requesting powerdown. When MCU requests powerdown with SCLK_HF as source, then WUC will switch over to this clock source during powerdown, and automatically switch back to SCLK_HF when MCU is no longer requesting powerdown and system is back in active mode.

AUX Clock Management This register contains bitfields that are relevant for setting up the clock to the AUX domain.

[12:11] When AUX requests powerdown with SCLK_HF as source, then WUC will switch over to this clock source during powerdown, and automatically switch back to SCLK_HF when AUX system is back in active mode

[10:8] Select the AUX clock divider for SCLK_HF NB: It is not supported to change the AUX clock divider while SCLK_HF is active source for AUX

[2:0] Selects the clock source for AUX: NB: Switching the clock source is guaranteed to be glitchless

MCU Configuration This register contains power management related bitfields for the MCU domain.

[3:0] MCU SRAM is partitioned into 4 banks . This register controls which of the banks that has retention during MCU power off

AUX Configuration This register contains power management related signals for the AUX domain.

[0:0] This bit controls retention mode for the AUX_RAM:BANK0: 0: Retention is disabled 1: Retention is enabled NB: If retention is disabled, the AUX_RAM will be powered off when it would otherwise be put in retention mode

AUX Control This register contains events and control signals for the AUX domain.

[31:31] Reset request for AUX. Writing 1 to this register will assert reset to AUX. The reset will be held until the bit is cleared again. 0: AUX reset pin will be deasserted 1: AUX reset pin will be asserted

[2:2] Enables (1) or disables (0) AUX_SCE execution. AUX_SCE execution will begin when AUX Domain is powered and either this or AUX_SCE:CTL.CLK_EN is set. Setting this bit will assure that AUX_SCE execution starts as soon as AUX power domain is woken up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX power domain has been off) 0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0 1: AUX_SCE execution is enabled.

[1:1] Writing 1 sets the software event to the AUX domain, which can be read through AUX_WUC:WUEVFLAGS.AON_SW. This event is normally cleared by AUX_SCE through the AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0 to this register. Reading 0 means that there is no outstanding software event for AUX. Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from AUX.

[0:0] Forces the AUX domain into active mode, overriding the requests from AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL. Note that an ongoing AUX_WUC:PWROFFREQ will complete before this bit will set the AUX domain into active mode. MCU must set this bit in order to access the AUX peripherals. The AUX domain status can be read from PWRSTAT.AUX_PD_ON 0: AUX is allowed to Power Off, Power Down or Disconnect. 1: AUX Power OFF, Power Down or Disconnect requests will be overruled

Power Status This register is used to monitor various power management related signals in AON. Most signals are for test, calibration and debug purpose only, and others can be used to detect that AUX or JTAG domains are powered up.

[9:9] Indicates the AUX powerdown state when AUX domain is powered up. 0: Active mode 1: AUX Powerdown request has been granted

[6:6] Indicates JTAG power state: 0: JTAG is powered off 1: JTAG is powered on

[5:5] Indicates AUX power state: 0: AUX is not ready for use ( may be powered off or in power state transition ) 1: AUX is powered on, connected to bus and ready for use,

[4:4] Indicates MCU power state: 0: MCU Power sequencing is not yet finalized and MCU_AONIF registers may not be reliable 1: MCU Power sequencing is finalized and all MCU_AONIF registers are reliable

[2:2] Indicates that AUX Bus is connected: 0: AUX bus is not connected 1: AUX bus is connected ( idle_ack = 0 )

[1:1] Indicates Reset Done from AUX: 0: AUX is being reset 1: AUX reset is released

Shutdown Control This register contains bitfields required for entering shutdown mode

[0:0] Writing a 1 to this bit forces a shutdown request to be registered and all I/O values to be latched - in the PAD ring, possibly enabling I/O wakeup. Writing 0 will cancel a registered shutdown request and open th I/O latches residing in the PAD ring. A registered shutdown request takes effect the next time power down conditions exists. At this time, the will not enter Powerdown mode, but instead it will turn off all internal powersupplies, effectively putting the device into Shutdown mode.

Control 0 This register contains various chip level control and debug bitfields.

[8:8] Controls whether MCU and AUX requesting to be powered off will enable a transition to powerdown: 0: Enabled 1: Disabled

Control 1 This register contains various chip level control and debug bitfields.

[1:1] Indicates source of last MCU Voltage Domain warm reset request: 0: MCU SW reset 1: JTAG reset This bit can only be cleared by writing a 1 to it

[0:0] Indicates type of last MCU Voltage Domain reset: 0: Last MCU reset was not a warm reset 1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated in MCU_RESET_SRC) This bit can only be cleared by writing a 1 to it

Recharge Controller Configuration This register sets all relevant patameters for controlling the recharge algorithm.

[31:31] Enable adaptive recharge Note: Recharge can be turned completely of by setting MAX_PER_E=7 and MAX_PER_M=31 and this bitfield to 0

[23:20] Gain factor for adaptive recharge algorithm period_new=period * ( 1+/-(2^-C1+2^-C2) ) Valid values for C2 is 2 to 10 Note: Rounding may cause adaptive recharge not to start for very small values of both Gain and Initial period. Criteria for algorithm to start is MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1

[19:16] Gain factor for adaptive recharge algorithm period_new=period * ( 1+/-(2^-C1+2^-C2) ) Valid values for C1 is 1 to 10 Note: Rounding may cause adaptive recharge not to start for very small values of both Gain and Initial period. Criteria for algorithm to start is MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1

[15:11] This register defines the maximum period that the recharge algorithm can take, i.e. it defines the maximum number of cycles between 2 recharges. The maximum number of cycles is specified with a 5 bit mantissa and 3 bit exponent: MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E This field sets the mantissa of MAXCYCLES

[10:8] This register defines the maximum period that the recharge algorithm can take, i.e. it defines the maximum number of cycles between 2 recharges. The maximum number of cycles is specified with a 5 bit mantissa and 3 bit exponent: MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E This field sets the exponent MAXCYCLES

[7:3] Number of 32 KHz clocks between activation of recharge controller For recharge algorithm, PERIOD is the initial period when entering powerdown mode. The adaptive recharge algorithm will not change this register PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent: This field sets the Mantissa of the Period. PERIOD=(PER_M*16+15)*2^PER_E

[2:0] Number of 32 KHz clocks between activation of recharge controller For recharge algorithm, PERIOD is the initial period when entering powerdown mode. The adaptive recharge algorithm will not change this register PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent: This field sets the Exponent of the Period. PERIOD=(PER_M*16+15)*2^PER_E

Recharge Controller Status This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug.

[19:16] The last 4 VDDR samples, bit 0 being the newest. The register is being updated in every recharge period with a shift left, and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be shifted in.

[15:0] The maximum value of recharge period seen with VDDR>threshold. The VDDR voltage is compared against the threshold voltage at just before each recharge. If VDDR is above threshold, MAX_USED_PER is updated with max ( current recharge peride; MAX_USED_PER ) This way MAX_USED_PER can track the recharge period where VDDR is decharged to the threshold value. We can therefore use the value as an indication of the leakage current during recharge. This bitfield is cleared to 0 when writing this register.

Oscillator Configuration This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode.

[7:3] Number of 32 KHz clocks between oscillator amplitude calibrations. When this counter expires, an oscillator amplitude compensation is triggered immediately in Active mode. When this counter expires in Powerdown mode an internal flag is set such that the amplitude compensation is postponed until the next recharge occurs. The Period will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent PERIOD=(PER_M*16+15)*2^PER_E This field sets the mantissa Note: Oscillator amplitude calibration is turned of when both this bitfield and PER_E are set to 0

[2:0] Number of 32 KHz clocks between oscillator amplitude calibrations. When this counter expires, an oscillator amplitude compensation is triggered immediately in Active mode. When this counter expires in Powerdown mode an internal flag is set such that the amplitude compensation is postponed until the next recharge occurs. The Period will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent PERIOD=(PER_M*16+15)*2^PER_E This field sets the exponent Note: Oscillator amplitude calibration is turned of when both PER_M and this bitfield are set to 0

JTAG Configuration This register contains control for configuration of the JTAG domain,- hereunder access permissions for each TAP.

[8:8] Controls JTAG PowerDomain power state: 0: Controlled exclusively by debug subsystem. (JTAG Powerdomain will be powered off unless a debugger is attached) 1: JTAG Power Domain is forced on, independent of debug subsystem. NB: The reset value causes JTAG Power Domain to be powered on by default. Software must clear this bit to turn off the JTAG Power Domain

JTAG USERCODE Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem.

[31:0] 32-bit JTAG USERCODE register feeding main JTAG TAP NB: This field can be locked

Current Source Strength and trim control for current source. Only to be used through TI provided API.

[7:2] Adjust current from current source. Output currents may be combined to get desired total current.

[0:0] Current source enable

Comparator Control COMPA and COMPB comparators. Only to be used through TI provided API.

[7:7] Enables 400kohm resistance from COMPA reference node to ground. Used with COMPA_REF_CURR_EN to generate voltage reference for cap-sense.

[6:6] Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for cap-sense.

[5:3] COMPB voltage reference trim temperature coded:

[2:2] COMPB enable

[0:0] COMPA enable

ADC Control 0 ADC Sample Control. Only to be used through TI provided API.

[7:7] ADC Sampling mode: 0: Synchronous mode 1: Asynchronous mode The ADC does a sample-and-hold before conversion. In synchronous mode the sampling starts when the ADC clock detects a rising edge on the trigger signal. Jitter/uncertainty will be inferred in the detection if the trigger signal originates from a domain that is asynchronous to the ADC clock. SMPL_CYCLE_EXP determines the the duration of sampling. Conversion starts immediately after sampling ends. In asynchronous mode the sampling is continuous when enabled. Sampling ends and conversion starts immediately with the rising edge of the trigger signal. Sampling restarts when the conversion has finished. Asynchronous mode is useful when it is important to avoid jitter in the sampling instant of an externally driven signal

[6:3] Controls the sampling duration before conversion when the ADC is operated in synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us.

[1:1] Reset ADC digital subchip, active low. ADC must be reset every time it is reconfigured. 0: Reset 1: Normal operation

[0:0] ADC Enable 0: Disable 1: Enable

ADC Control 1 ADC Comparator Control. Only to be used through TI provided API.

ADC Reference 0 Control reference used by the ADC. Only to be used through TI provided API.

[6:6] Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0. Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time)

[3:3] ADC reference source: 0: Fixed reference = 4.3V 1: Relative reference = VDDS

[0:0] ADC reference module enable: 0: ADC reference module powered down 1: ADC reference module enabled

ADC Reference 1 Control reference used by the ADC. Only to be used through TI provided API.

[5:0] Trim output voltage of ADC fixed reference (64 steps, 2's complement). Applies only for ADCREF0.SRC = 0. Examples: 0x00 - nominal voltage 1.43V 0x01 - nominal + 0.4% 1.435V 0x3F - nominal - 0.4% 1.425V 0x1F - maximum voltage 1.6V 0x20 - minimum voltage 1.3V

General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1

[7:0] Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].

Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1

[15:14] Select mode for AUXIO[8i+7].

[13:12] Select mode for AUXIO[8i+6].

[11:10] Select mode for AUXIO[8i+5].

[9:8] Select mode for AUXIO[8i+4].

[7:6] Select mode for AUXIO[8i+3].

[5:4] Select mode for AUXIO[8i+2].

[3:2] Select mode for AUXIO[8i+1].

[1:0] Select mode for AUXIO[8i+0].

General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and I = 1 for AUX_AIODIO1.

[7:0] Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n value is old.

General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1.

[7:0] Write 1 to bit index n in this bit vector to set GPIODOUT bit n. Read value is 0.

General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1.

[7:0] Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. Read value is 0.

General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1.

[7:0] Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. Read value is 0.

General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and I = 1 for AUX_AIODIO1.

[7:0] Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]. Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n]. You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN. You must disable the digital input buffer for analog input or pins that float to avoid current leakage.

General Purpose Input Output Data Out The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1

[7:0] Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].

Input Output Mode This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1

[15:14] Select mode for AUXIO[8i+7].

[13:12] Select mode for AUXIO[8i+6].

[11:10] Select mode for AUXIO[8i+5].

[9:8] Select mode for AUXIO[8i+4].

[7:6] Select mode for AUXIO[8i+3].

[5:4] Select mode for AUXIO[8i+2].

[3:2] Select mode for AUXIO[8i+1].

[1:0] Select mode for AUXIO[8i+0].

General Purpose Input Output Data In This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and I = 1 for AUX_AIODIO1.

[7:0] Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n value is old.

General Purpose Input Output Data Out Set Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1.

[7:0] Write 1 to bit index n in this bit vector to set GPIODOUT bit n. Read value is 0.

General Purpose Input Output Data Out Clear Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1.

[7:0] Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. Read value is 0.

General Purpose Input Output Data Out Toggle Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and i = 1 for AUX_AIODIO1.

[7:0] Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. Read value is 0.

General Purpose Input Output Digital Input Enable This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0 and I = 1 for AUX_AIODIO1.

[7:0] Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]. Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n]. You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN. You must disable the digital input buffer for analog input or pins that float to avoid current leakage.

ADC Control Configuration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion.

[13:13] Select active polarity for START_SRC event.

[12:8] Select ADC trigger event source from the asynchronous AUX event bus. Set START_SRC to NO_EVENT if you want to trigger the ADC manually through ADCTRIG.START.

[1:0] ADC interface command. Non-enumerated values are not supported. The written value is returned when read.

ADC FIFO Status FIFO can hold up to four ADC samples.

[4:4] FIFO overflow flag. 0: FIFO has not overflowed. 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO write pointer is static. It is not possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag.

[3:3] FIFO underflow flag. 0: FIFO has not underflowed. 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. When the flag is set, the ADC FIFO read pointer is static. Read returns the previous sample that was read. Flush FIFO to clear the flag.

[2:2] FIFO full flag. 0: FIFO is not full, there is less than 4 samples in the FIFO. 1: FIFO is full, there are 4 samples in the FIFO. When the flag is set, it is not possible to add more samples to the ADC FIFO. An attempt to add samples sets the OVERFLOW flag.

[1:1] FIFO almost full flag. 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL flag is also asserted in the latter case. 1: There are 3 samples in the FIFO, there is room for one more sample.

[0:0] FIFO empty flag. 0: FIFO contains one or more samples. 1: FIFO is empty. When the flag is set, read returns the previous sample that was read and sets the UNDERFLOW flag.

ADC FIFO

[11:0] FIFO data. Read: Get oldest ADC sample from FIFO. Write: Write dummy sample to FIFO. This is useful for code development when you do not have real ADC samples.

ADC Trigger

[0:0] Manual ADC trigger. 0: No effect. 1: Single ADC trigger. To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to avoid conflict with event-driven ADC trigger.

Current Source Control

[0:0] ISRC reset control. 0: ISRC drives 0 uA. 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN.

Control 0 Controls clock source selects

[31:31] Set based on the accurate high frequency XTAL.

[16:16] 0: Default - Switching of HF clock source is disabled . 1: Allows switching of sclk_hf source. Provided to prevent switching of the SCLK_HF source when running from flash (a long period during switching could corrupt flash). When sclk_hf switching is disabled, a new source can be started when SCLK_HF_SRC_SEL is changed, but the switch will not occur until this bit is set. This bit should be set to enable clock switching after STAT0.PENDINGSCLKHFSWITCHING indicates the new HF clock is ready. When switching completes (also indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be disabled to prevent flash corruption. Switching should not be enabled when running from flash.

[10:10] Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock. 0: Use 32kHz XOSC as xosc_lf clock source 1: Use digital input (from AON) as xosc_lf clock source. This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf as the sclk_lf source. The muxing performed by this bit is not glitch free. The following procedure must be followed when changing this field to avoid glitches on sclk_lf. 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock source. 2) Set or clear this bit to bypass or not bypass the xosc_lf. 3) Set SCLK_LF_SRC_SEL to use xosc_lf. It is recommended that either the rcosc_hf or xosc_hf (whichever is currently active) be selected as the source in step 1 above. This provides a faster clock change.

[9:9] Enable clock loss detection and hence the indicators to system controller. Checks both SCLK_HF and SCLK_LF clock loss indicators. 0: Disable 1: Enable Clock loss detection must be disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed.

[8:7] Source select for aclk_tdc. 00: RCOSC_HF (48MHz) 01: RCOSC_HF (24MHz) 10: XOSC_HF (24MHz) 11: Not used

[6:5] Source select for aclk_ref 00: RCOSC_HF derived (31.25kHz) 01: XOSC_HF derived (31.25kHz) 10: RCOSC_LF (32kHz) 11: XOSC_LF (32.768kHz)

[3:2] Source select for sclk_lf

[0:0] Source select for sclk_hf. XOSC option is supported for test and debug only and should be used when the XOSC_HF is running.

Control 1 This register contains OSC_DIG configuration

RADC External Configuration

Amplitude Compensation Control

Amplitude Compensation Threshold 1 This register contains threshold values for amplitude compensation algorithm

Amplitude Compensation Threshold 2 This register contains threshold values for amplitude compensation algorithm.

Analog Bypass Values 1

Analog Test Control

[29:29] Enable 32 kHz clock to AUX_COMPB.

ADC Doubler Nanoamp Control

XOSCHF Control

Low Frequency Oscillator Control

RCOSCHF Control

Status 0 This register contains status signals from OSC_DIG

[30:29] Indicates source for the sclk_lf

[28:28] Indicates source for the sclk_hf

[22:22] RCOSC_HF_EN

[21:21] RCOSC_LF_EN

[20:20] XOSC_LF_EN

[19:19] CLK_DCDC_RDY

[18:18] CLK_DCDC_RDY_ACK

[17:17] Indicates sclk_hf is lost

[16:16] Indicates sclk_lf is lost

[15:15] Indicates that XOSC_HF is enabled.

[13:13] Indicates that the 48MHz clock from the DOUBLER is enabled. It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal).

[11:11] XOSC_HF_LP_BUF_EN

[10:10] XOSC_HF_HP_BUF_EN

[8:8] ADC_THMET

[7:7] indicates when adc_data is ready.

[6:1] adc_data

[0:0] Indicates when sclk_hf is ready to be switched

Status 1 This register contains status signals from OSC_DIG

[31:28] AMPCOMP FSM State

[27:22] OSC amplitude during HPM_UPDATE state. When amplitude compensation of XOSC_HF is enabled in high performance mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value.

[21:16] OSC amplitude during LPM_UPDATE state When amplitude compensation of XOSC_HF is enabled in low power mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value.

[15:15] force_rcosc_hf

[14:14] SCLK_HF_EN

[13:13] SCLK_MF_EN

[12:12] ACLK_ADC_EN

[11:11] ACLK_TDC_EN

[10:10] ACLK_REF_EN

[9:9] CLK_CHP_EN

[8:8] CLK_DCDC_EN

[7:7] SCLK_HF_GOOD

[6:6] SCLK_MF_GOOD

[5:5] SCLK_LF_GOOD

[4:4] ACLK_ADC_GOOD

[3:3] ACLK_TDC_GOOD

[2:2] ACLK_REF_GOOD

[1:1] CLK_CHP_GOOD

[0:0] CLK_DCDC_GOOD

Status 2 This register contains status signals from AMPCOMP FSM

[31:26] DC Bias read by RADC during SAR mode The value is an unsigned integer. It is used for debug only.

[25:25] Indication of threshold is met for hpm_ramp1

[24:24] Indication of threshold is met for hpm_ramp2

[23:23] Indication of threshold is met for hpm_ramp3

[15:12] xosc_hf amplitude compensation FSM This is identical to STAT1.RAMPSTATE. See that description for encoding.

[3:3] ampcomp_req

[2:2] amplitude of xosc_hf is within the required threshold (set by DDI). Not used for anything just for debug/status

[1:1] frequency of xosc_hf is good to use for the digital clocks

[0:0] frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer.

Vector Configuration 0 AUX_SCE wakeup vector 0 and 1 configuration

[14:14] Vector 1 trigger event polarity. To manually trigger vector 1 execution: - AUX_SCE must sleep. - Set VEC1_EV to a known static value. - Toggle VEC1_POL twice.

[13:13] Vector 1 trigger enable. When enabled, VEC1_EV event with VEC1_POL polarity triggers a jump to vector # 1 when AUX_SCE sleeps. Lower vectors (0) have priority.

[12:8] Select vector 1 trigger source event.

[6:6] Vector 0 trigger event polarity. To manually trigger vector 0 execution: - AUX_SCE must sleep. - Set VEC0_EV to a known static value. - Toggle VEC0_POL twice.

[5:5] Vector 0 trigger enable. When enabled, VEC0_EV event with VEC0_POL polarity triggers a jump to vector # 0 when AUX_SCE sleeps.

[4:0] Select vector 0 trigger source event.

Vector Configuration 1 AUX_SCE event vectors 2 and 3 configuration

[14:14] Vector 3 trigger event polarity. To manually trigger vector 3 execution: - AUX_SCE must sleep. - Set VEC3_EV to a known static value. - Toggle VEC3_POL twice.

[13:13] Vector 3 trigger enable. When enabled, VEC3_EV event with VEC3_POL polarity triggers a jump to vector # 3 when AUX_SCE sleeps. Lower vectors (0, 1, and 2) have priority.

[12:8] Select vector 3 trigger source event.

[6:6] Vector 2 trigger event polarity. To manually trigger vector 2 execution: - AUX_SCE must sleep. - Set VEC2_EV to a known static value. - Toggle VEC2_POL twice.

[5:5] Vector 2 trigger enable. When enabled, VEC2_EV event with VEC2_POL polarity triggers a jump to vector # 2 when AUX_SCE sleeps. Lower vectors (0 and 1) have priority.

[4:0] Select vector 2 trigger source event.

Sensor Controller Engine Wait Event Selection Configuration of this register controls bit index 7 in AUX_SCE:WUSTAT.EV_SIGNALS. This bit can be used by AUX_SCE WEV0, WEV1, BEV0 and BEV1 instructions

[4:0] Select event source to connect to AUX_SCE:WUSTAT.EV_SIGNALS bit 7.

Events To AON Flags This register contains a collection of event flags routed to AON_EVENT. To clear an event flag, write to EVTOAONFLAGSCLR or write 0 to event flag in this register.

[8:8] This event flag is set when level selected by EVTOAONPOL.TIMER1_EV occurs on EVSTAT0.TIMER1_EV.

[7:7] This event flag is set when level selected by EVTOAONPOL.TIMER0_EV occurs on EVSTAT0.TIMER0_EV.

[6:6] This event flag is set when level selected by EVTOAONPOL.TDC_DONE occurs on EVSTAT0.TDC_DONE.

[5:5] This event flag is set when level selected by EVTOAONPOL.ADC_DONE occurs on EVSTAT0.ADC_DONE.

[4:4] This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on EVSTAT0.AUX_COMPB.

[3:3] This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on EVSTAT0.AUX_COMPA.

[2:2] This event flag is set when software writes a 1 to SWEVSET.SWEV2.

[1:1] This event flag is set when software writes a 1 to SWEVSET.SWEV1.

[0:0] This event flag is set when software writes a 1 to SWEVSET.SWEV0.

Events To AON Polarity Event source polarity configuration for EVTOAONFLAGS.

[8:8] Select the level of EVSTAT0.TIMER1_EV that sets EVTOAONFLAGS.TIMER1_EV.

[7:7] Select the level of EVSTAT0.TIMER0_EV that sets EVTOAONFLAGS.TIMER0_EV.

[6:6] Select level of EVSTAT0.TDC_DONE that sets EVTOAONFLAGS.TDC_DONE.

[5:5] Select the level of EVSTAT0.ADC_DONE that sets EVTOAONFLAGS.ADC_DONE.

[4:4] Select the edge of EVSTAT0.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB.

[3:3] Select the edge of EVSTAT0.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA.

Direct Memory Access Control

[2:2] UDMA0 Request mode

[1:1] uDMA ADC interface enable. 0: Disable UDMA0 interface to ADC. 1: Enable UDMA0 interface to ADC.

[0:0] Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO data.

Software Event Set Set software event flags from AUX domain to AON and MCU domains. CPUs in MCU domain can read the event flags from EVTOAONFLAGS and clear them in EVTOAONFLAGSCLR. Use of these event flags is software-defined.

[2:2] Software event flag 2. 0: No effect. 1: Set software event flag 2.

[1:1] Software event flag 1. 0: No effect. 1: Set software event flag 1.

[0:0] Software event flag 0. 0: No effect. 1: Set software event flag 0.

Event Status 0 Register holds events 0 thru 15 of the 32-bit event bus that is synchronous to AUX clock. The following subscribers use the asynchronous version of events in this register. - AUX_ANAIF. - AUX_TDC.

[15:15] AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2.

[14:14] AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1.

[13:13] AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0.

[12:12] AON_EVENT:AUXWUSEL.WU2_EV OR AON_EVENT:AUXWUSEL.WU1_EV OR AON_EVENT:AUXWUSEL.WU0_EV

[11:11] AON_WUC:AUXCTL.SWEV

[10:10] Observation input 1 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL1.

[9:9] Observation input 0 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by IOC:OBSAUXOUTPUT.SEL_MISC.

[8:8] AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL

[7:7] AUX_ANAIF ADC conversion done event.

[6:6] See AUX_SMPH:AUTOTAKE.SMPH_ID for description.

[5:5] AUX_TIMER1_EV event, see AUX_TIMER:T1TARGET for description.

[4:4] AUX_TIMER0_EV event, see AUX_TIMER:T0TARGET for description.

[3:3] AUX_TDC:STAT.DONE

[2:2] Comparator B output

[1:1] Comparator A output

[0:0] AON_RTC:EVFLAGS.CH2

Event Status 1 Current event source levels, 31:16

[15:15] The logical function for this event is configurable. When DMACTL.EN = 1 : Event = UDMA0 Channel 7 done event OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW When DMACTL.EN = 0 : Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW Bit 7 in UDMA0:DONEMASK must be 0.

[14:14] Event from EVENT configured by EVENT:AUXSEL0.

[13:13] TDC reference clock. It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_WUC:REFCLKCTL.REQ.

[12:12] AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7.

[11:11] AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6.

[10:10] AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5.

[9:9] AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4.

[8:8] AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3.

[7:7] AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2.

[6:6] AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1.

[5:5] AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0.

[4:4] AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7.

[3:3] AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6.

[2:2] AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5.

[1:1] AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4.

[0:0] AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3.

Event To MCU Polarity Event source polarity configuration for EVTOMCUFLAGS.

[10:10] Select the event source level that sets EVTOMCUFLAGS.ADC_IRQ.

[9:9] Select the event source level that sets EVTOMCUFLAGS.OBSMUX0.

[8:8] Select the event source level that sets EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL.

[7:7] Select the event source level that sets EVTOMCUFLAGS.ADC_DONE.

[6:6] Select the event source level that sets EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE.

[5:5] Select the event source level that sets EVTOMCUFLAGS.TIMER1_EV.

[4:4] Select the event source level that sets EVTOMCUFLAGS.TIMER0_EV.

[3:3] Select the event source level that sets EVTOMCUFLAGS.TDC_DONE.

[2:2] Select the event source level that sets EVTOMCUFLAGS.AUX_COMPB.

[1:1] Select the event source level that sets EVTOMCUFLAGS.AUX_COMPA.

[0:0] Select the event source level that sets EVTOMCUFLAGS.AON_WU_EV.

Events to MCU Flags This register contains a collection of event flags routed to MCU domain. To clear an event flag, write to EVTOMCUFLAGSCLR or write 0 to event flag in this register. Follow procedure described in AUX_SYSIF:WUCLR to clear AUX_WU_EV event flag.

[10:10] This event flag is set when level selected by EVTOMCUPOL.ADC_IRQ occurs on EVSTAT0.ADC_IRQ.

[9:9] This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs on EVSTAT0.MCU_OBSMUX0.

[8:8] This event flag is set when level selected by EVTOMCUPOL.ADC_FIFO_ALMOST_FULL occurs on EVSTAT0.ADC_FIFO_ALMOST_FULL.

[7:7] This event flag is set when level selected by EVTOMCUPOL.ADC_DONE occurs on EVSTAT0.ADC_DONE.

[6:6] This event flag is set when level selected by EVTOMCUPOL.SMPH_AUTOTAKE_DONE occurs on EVSTAT0.SMPH_AUTOTAKE_DONE.

[5:5] This event flag is set when level selected by EVTOMCUPOL.TIMER1_EV occurs on EVSTAT0.TIMER1_EV.

[4:4] This event flag is set when level selected by EVTOMCUPOL.TIMER0_EV occurs on EVSTAT0.TIMER0_EV.

[3:3] This event flag is set when level selected by EVTOMCUPOL.TDC_DONE occurs on EVSTAT0.TDC_DONE.

[2:2] This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on EVSTAT0.AUX_COMPB.

[1:1] This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on EVSTAT0.AUX_COMPA.

[0:0] This event flag is set when level selected by EVTOMCUPOL.AON_WU_EV occurs on the reduction-OR of the AUX_EVCTL:EVSTAT0.RTC_CH2_EV, AUX_EVCTL:EVSTAT0.AON_SW, and AUX_EVCTL:EVSTAT0.AON_PROG_WU events.

Combined Event To MCU Mask Select event flags in EVTOMCUFLAGS that contribute to the AUX_COMB event to EVENT and system CPU. The AUX_COMB event is high as long as one or more of the included event flags are set.

[10:10] EVTOMCUFLAGS.ADC_IRQ contribution to the AUX_COMB event. 0: Exclude. 1: Include.

[9:9] EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. 0: Exclude. 1: Include.

[8:8] EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. 0: Exclude. 1: Include.

[7:7] EVTOMCUFLAGS.ADC_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include.

[6:6] EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include.

[5:5] EVTOMCUFLAGS.TIMER1_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include.

[4:4] EVTOMCUFLAGS.TIMER0_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include.

[3:3] EVTOMCUFLAGS.TDC_DONE contribution to the AUX_COMB event. 0: Exclude. 1: Include.

[2:2] EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. 0: Exclude 1: Include.

[1:1] EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. 0: Exclude. 1: Include.

[0:0] EVTOMCUFLAGS.AON_WU_EV contribution to the AUX_COMB event. 0: Exclude. 1: Include.

Vector Flags If a vector flag becomes 1 and AUX_SCE sleeps, AUX_SCE will wake up and execute the corresponding vector. The vector with the lowest index will execute first if multiple vectors flags are set. AUX_SCE must return to sleep to execute the next vector. During execution of a vector, AUX_SCE must clear the vector flag that triggered execution. Write 1 to bit index n in VECFLAGSCLR to clear vector flag n.

[3:3] Vector flag 3. The vector flag is set if the edge selected VECCFG1.VEC3_POL occurs on the event selected in VECCFG1.VEC3_EV. The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to VECFLAGSCLR.VEC3.

[2:2] Vector flag 2. The vector flag is set if the edge selected VECCFG1.VEC2_POL occurs on the event selected in VECCFG1.VEC2_EV. The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to VECFLAGSCLR.VEC2.

[1:1] Vector flag 1. The vector flag is set if the edge selected VECCFG0.VEC1_POL occurs on the event selected in VECCFG0.VEC1_EV. The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to VECFLAGSCLR.VEC1.

[0:0] Vector flag 0. The vector flag is set if the edge selected VECCFG0.VEC0_POL occurs on the event selected in VECCFG0.VEC0_EV. The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to VECFLAGSCLR.VEC0.

Events To MCU Flags Clear Clear event flags in EVTOMCUFLAGS. In order to clear a level sensitive event flag, the event must be deasserted.

[10:10] Write 1 to clear EVTOMCUFLAGS.ADC_IRQ. Read value is 0.

[9:9] Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. Read value is 0.

[8:8] Write 1 to clear EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. Read value is 0.

[7:7] Write 1 to clear EVTOMCUFLAGS.ADC_DONE. Read value is 0.

[6:6] Write 1 to clear EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. Read value is 0.

[5:5] Write 1 to clear EVTOMCUFLAGS.TIMER1_EV. Read value is 0.

[4:4] Write 1 to clear EVTOMCUFLAGS.TIMER0_EV. Read value is 0.

[3:3] Write 1 to clear EVTOMCUFLAGS.TDC_DONE. Read value is 0.

[2:2] Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. Read value is 0.

[1:1] Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. Read value is 0.

[0:0] Write 1 to clear EVTOMCUFLAGS.AON_WU_EV. Read value is 0.

Events To AON Clear Clear event flags in EVTOAONFLAGS. In order to clear a level sensitive event flag, the event must be deasserted.

[8:8] Write 1 to clear EVTOAONFLAGS.TIMER1_EV. Read value is 0.

[7:7] Write 1 to clear EVTOAONFLAGS.TIMER0_EV. Read value is 0.

[6:6] Write 1 to clear EVTOAONFLAGS.TDC_DONE. Read value is 0.

[5:5] Write 1 to clear EVTOAONFLAGS.ADC_DONE. Read value is 0.

[4:4] Write 1 to clear EVTOAONFLAGS.AUX_COMPB. Read value is 0.

[3:3] Write 1 to clear EVTOAONFLAGS.AUX_COMPA. Read value is 0.

[2:2] Write 1 to clear EVTOAONFLAGS.SWEV2. Read value is 0.

[1:1] Write 1 to clear EVTOAONFLAGS.SWEV1. Read value is 0.

[0:0] Write 1 to clear EVTOAONFLAGS.SWEV0. Read value is 0.

Vector Flags Clear Strobes for clearing flags in VECFLAGS.

[3:3] Clear vector flag 3. 0: No effect. 1: Clear VECFLAGS.VEC3. Read value is 0.

[2:2] Clear vector flag 2. 0: No effect. 1: Clear VECFLAGS.VEC2. Read value is 0.

[1:1] Clear vector flag 1. 0: No effect. 1: Clear VECFLAGS.VEC1. Read value is 0.

[0:0] Clear vector flag 0. 0: No effect. 1: Clear VECFLAGS.VEC0. Read value is 0.

Semaphore 0

[0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore.

Semaphore 1

[0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore.

Semaphore 2

[0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore.

Semaphore 3

[0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore.

Semaphore 4

[0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore.

Semaphore 5

[0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore.

Semaphore 6

[0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore.

Semaphore 7

[0:0] Request or release of semaphore. Request by read: 0: Semaphore not available. 1: Semaphore granted. Release by write: 0: Do not use. 1: Release semaphore.

Auto Take Sticky Request for Single Semaphore.

[2:0] Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until it is granted. When semaphore SMPH_ID is granted, event AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE becomes 1. The event becomes 0 when software releases the semaphore or writes a new value to SMPH_ID. To avoid corrupted semaphores: - Usage of this functionality must be restricted to one CPU core. - Software must wait until AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE is 1 before it writes a new value to SMPH_ID.

Control

[1:0] TDC commands.

Status

[7:7] TDC measurement saturation flag. 0: Conversion has not saturated. 1: Conversion stopped due to saturation. This field is cleared when a new measurement is started or when CLR_RESULT is written to CTL.CMD.

[6:6] TDC measurement complete flag. 0: TDC measurement has not yet completed. 1: TDC measurement has completed. This field clears when a new TDC measurement starts or when you write CLR_RESULT to CTL.CMD.